The invention is generally related to the field of semiconductor devices and more specifically to fabricating semiconductor devices having both analog and digital transistors.
As digital CMOS technology extended into the deep submicron range (e.g., 0.35 xcexcm and below), a device feature was developed to enable a much shorter channel length. This particular feature is a pocket implant. As shown in FIG. 1, pocket implants are used to provide a pocket region 16 of heavier doping of the same conductivity type as the channel/body 18 of the CMOS transistor 20. Pocket regions 16 extend further under the gate than drain extension regions 24. The drain 12 and source 14 regions are of opposite conductivity type with respect to the channel/body 18.
The pocket implant energy and anneal temperatures and times are designed such that the final dopant distribution serves to increase the channel doping concentration. The increased channel doping concentration reduces the depletion regions arising due to the electrostatic potential differences between source and the substrate and, more importantly, between the drain and the substrate. Such reduction in the depletion regions is known to result in improved short-channel characteristics, in particular, it leads to a reduced drain-induced barrier lowering or DIBL effect. Reduction in DIBL is critical to the ability to scale the MOSFET to smaller channel lengths without a concurrently sharp increase in subthreshold leakage. The key feature that has led to the use of pocket implants to increase the channel doping concentration in preference to the more conventional threshold voltage adjust implants is the fact that pocket implants are self-aligned to the gate. This means that the implant is largely blocked by the gate material so that the increased channel doping density due to the implant occurs only in the vicinity of the source and drain regions. One consequence of this is that the average doping density in the channel is low at long channel lengths and increases as the channel length is reduced. This is a desirable feature because the higher doping helps suppress the undesirable DIBL effect which is worse at smaller channel lengths, while at the longer lengths where such a high doping density is not needed the lower doping density results in higher inversion charge when the transistor gate is biased to turn on and conduct current. Higher inversion charge leads to a correspondingly higher drive current. Thus, over a statistical distribution of channel lengths one is able to obtain a higher drive current while maintaining a low off current.
High drive current increases the switching speed of digital logic gates, especially when the gates are required to drive large loads such as a long metal line. Low off current leads to a low standby power for CMOS logic circuits. Thus, MOSFETs designed with pocket implants are very attractive for high performance CMOS digital logic circuits. However, that is not true for many of the CMOS analog circuits. For example, the dc voltage gain of a CMOS differential amplifier is high for high values of gm/gds, where gm is the MOSFET""s small signal transconductance and gds is the MOSFET""s small-signal output conductance. Also, the standby power depends on the dc bias current, where the bias current value is designed for high gm/gds.
Unfortunately, it turns out that the high doping density localized near the drain region of MOSFETs, so typical of transistors with pocket implants, also makes it difficult to achieve a low gds. The self-aligned pocket implants naturally lead to a laterally nonuniform channel doping profile with the doping density low at the center and increasing to a pocket of high doping near the drain, as shown in FIG. 2. Such a profile causes an increasing potential barrier for the charge carriers (electrons for nMOS and holes for pMOS) to flow from the center to the drain. Being coincident with the pocket of high channel doping density in the vicinity of the drain, the magnitude of potential barrier is relatively easily modulated by the voltage Vds applied to the drain electrode. Increasing the magnitude of Vds (Normally, Vds greater than 0 for nMOS and Vds less than 0 for pMOS) lowers the barrier and vice versa. Consequently, the MOSFET output characteristic, which is the drain current Ids vs Vds at a constant gate bias of Vgs, fails to saturate as well as it otherwise should. Thus, generally, pocket implanted MOSFETs exhibit a relatively high slope (high gds) in the saturation region compared to conventional MOSFETs with a laterally uniform channel, as shown in FIG. 3. Furthermore, since the pocket and the accompanying potential barrier is present at long and short lengths, the rapid improvement (i.e., reduction) in gds with increasing channel length, commonly seen for conventional MOSFETs, is typically absent for MOSFETs with pocket implants. Thus, with pocket implanted devices one does not even have the option of increasing the gate length to achieve the high gm/gds needed for acceptable analog performance.
There is a need in modern technologies to be able to build advanced circuitry of both a digital and analog nature on the same integrated circuit. Therefore, there is a need for a method of producing transistors that are more analog friendly along with digital transistors in the same monolithic solution.
An embodiment of the invention solves the problem of forming analog and digital transistors at the same time by providing a flatter surface concentration on the drain end of the channel doping profile for the analog transistors. Thus, the analog transistors exhibit a linear saturation characteristic with linearly increasing drain voltage. The low voltage digital transistors retain the pocket implants for fast charging and minimal drain resistance.
Another embodiment of the invention develops an optimized process flow for combining analog and digital transistors.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.